Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.
Maintained by: Stephen Van Berg
Approved by: rworkman
(the SlackBuild does not include the source)