SlackBuilds Repository

14.0 > Academic > verilog (0.9.4)

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.

Maintained by: Stephen Van Berg
Keywords: verilog,hdl,eda,geda,vpp,icarus

Homepage:
http://www.icarus.com/eda/verilog/

Source Downloads:
verilog-0.9.4.tar.gz (013f1397338fd984ec711250408e43a6)

Download SlackBuild:
verilog.tar.gz
verilog.tar.gz.asc (FAQ)

(the SlackBuild does not include the source)

Individual Files:
README
slack-desc
verilog.SlackBuild
verilog.info

See our HOWTO for instructions on how to use the contents of this repository.

Access to the repository is available via:
ftp git cgit http rsync

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