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15.0 > Development > adms (2.3.7)

ADMS is a code generator for the Verilog-AMS language

ADMS is a code generator that converts electrical compact
device models specified in high-level description language into
ready-to-compile C code for the API of spice simulators. Based on
transformations specified in XML language, ADMS transforms Verilog-AMS
code into other target languages.

This requires: perl-xml-libxml

Maintained by: Fellype do Nascimento
Keywords: verilog-ams,qucs,spice
ChangeLog: adms