ADMS is a code generator for the Verilog-AMS language
ADMS is a code generator that converts electrical compact
device models specified in high-level description language into
ready-to-compile C code for the API of spice simulators. Based on
transformations specified in XML language, ADMS transforms Verilog-AMS
code into other target languages.
This requires: perl-xml-libxml
Maintained by: Fellype do Nascimento
Keywords: verilog-ams,qucs,spice
ChangeLog: adms
Homepage:
http://sourceforge.net/projects/mot-adms/
Download SlackBuild:
adms.tar.gz
adms.tar.gz.asc (FAQ)
(the SlackBuild does not include the source)
Individual Files: |
README |
adms.SlackBuild |
adms.info |
slack-desc |
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