DRAMSim2 is a cycle accurate model of a DRAM memory controller, the
DRAM modules which comprise system storage, and the bus by which they
communicate. All major components in a modern memory system are
modeled as their own respective objects within the source, including:
ranks, banks, command queue, the memory controller, etc.
For setting the DEBUG mode use the enviroment variable DEBUG=1
Maintained by: William PC
Keywords: memory simulator,memory modeling,simulation
ChangeLog: DRAMSim2
Homepage:
https://github.com/umd-memsys/DRAMSim2
Download SlackBuild:
DRAMSim2.tar.gz
DRAMSim2.tar.gz.asc (FAQ)
(the SlackBuild does not include the source)
Individual Files: |
DRAMSim2.SlackBuild |
DRAMSim2.info |
README |
slack-desc |
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