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15.0 > Academic > verilator (5.050)

Verilator is the fastest free Verilog HDL simulator.

Verilator is invoked with parameters similar to GCC or Synopsys's
VCS. It "Verilates" the specified synthesizable Verilog or
SystemVerilog code by reading it, performing lint checks, and
optionally inserting assertion checks and coverage-analysis points.
It outputs single- or multi-threaded .cpp and .h files,
the "Verilated" code.

Optional runtime dependencies:

* gtkwave for FST tracing (and waveform viewing)
* z3 for constrained randomization
* SystemC for SystemC support

This requires: sphinx-rtd-theme, Sphinx

Maintained by: Nick Smallbone
Keywords: verilator,verilog,HDL
ChangeLog: verilator