SlackBuilds Repository

15.0 > Academic > verilog (11.0)

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.

Maintained by: Stephen Van Berg
Keywords: verilog,hdl,eda,geda,vpp,icarus
ChangeLog: verilog


Source Downloads:
verilog-11.0.tar.gz (a3f7a618a4f499244ec6ee928574f03d)

Download SlackBuild:
verilog.tar.gz.asc (FAQ)

(the SlackBuild does not include the source)

Individual Files:

Validated for Slackware 15.0

See our HOWTO for instructions on how to use the contents of this repository.

Access to the repository is available via:
ftp git cgit http rsync

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